I. Field of the Disclosure
The technology of the disclosure relates generally storing data in computer memory, and more particularly to accessing compressed and uncompressed memory lines in memory of a processor-based system.
II. Background
Computing devices are prevalent in society. These devices may include servers, computers, cellular telephones, portable digital assistants (“PDAs”), portable game consoles, palmtop computers, and other electronic devices. Computing devices conventionally include a processor-based system that performs computational tasks in a wide variety of applications. The processor-based system may be included with other integrated circuits designed to work together in a system-on-a-chip (“SoC”), to deliver functionality to a user. A typical processor-based system includes one or more processors that execute software instructions. The software instructions instruct a processor to fetch data from a location in a memory, perform one or more processor operations using the fetched data, and generate a stored result. As examples, software instructions can be stored in a system or main memory. The software instructions can also be fetched and stored in a cache memory for faster fetching. For example, the cache memory (“cache”) can be a cache memory local to the processor, a shared local cache among processors in a processor block, a shared cache among multiple processor blocks, or a main memory of the processor-based system. In this regard, the size of the memory lines accessed from system or main memory may be the size of the cache lines to allow accessed memory lines in system or main memory for a memory access to fill up a cache line in cache memory for efficiency purposes.
FIG. 1 is a schematic diagram of an exemplary SoC 100 that includes a processor-based system 102. The processor-based system 102 includes a plurality of processor blocks 104(1)-104(N), wherein ‘N’ is equal to any number of processor blocks 104 desired. Each processor block 104(1)-104(N) contains two processors 106(1), 106(2) and a shared level 2 (L2) cache 108(1)-108(N), respectively. A shared level 3 (L3) cache 110 is also provided for storing cached data that is used by any of, or shared among, each of the processor blocks 104(1)-104(N). An internal system bus 112 is provided that allows each of the processor blocks 104(1)-104(N) to access the shared L3 cache 110 as well as other shared resources including a memory controller 114 for accessing a main, external memory (e.g., double-rate dynamic random access memory (DRAM) (DDR)), peripherals 116, other storage 118, an express peripheral component interconnect (PCI) interface 120, a direct memory access (DMA) controller 122, and an integrated memory controller (IMC) 124.
As processor-based systems increase in complexity and performance, the memory capacity requirements of memory may also increase. However, providing additional memory capacity in a processor-based system increases cost and area needed for memory on an integrated circuit. Memory capacity compression, such as cache line level compression, where each memory line the size of cache lines is independently compressed, may be employed transparent to the operating system to increase the effective memory capacity of the processor-based system without increasing physical memory capacity. However, addressing compressed lines in memory can increase memory read access latency, because processing time is incurred uncompressing the compressed data in response to a memory read access. Further, writing compressed data to memory can increase memory write latency, because processing time is incurred in compressing the data to be written into memory. Still further, data compression can increase memory management complexity, because the processor maps logical memory addresses of fixed-size cache lines, to corresponding physical memory addresses that store variable size compressed cache lines in memory corresponding to the fixed size cache lines. As a result, for example, accessing a particular cache line in memory may require access to metadata in the memory and an additional layer of address computation to determine the location of the compressed cache line in memory corresponding to the particular cache line. This can increase complexity, cost, and latency to a processor-based system employing memory capacity compression.